1. Field of the Invention
This invention relates to the field of optimizing compilers for computer systems. Specifically, this invention is a new and useful optimization method, apparatus and computer program product for optimizing computations using a register stack instead of named registers.
2. Background
Many modem computer architectures use names to identify specific registers. Optimizing compilers have developed many techniques to optimize the use of such named registers. Some computer architectures also use a register stack for some registers. Intel.RTM. processors use a register stack for floating point operations. This register stack organization is described by Chapter 7 of Intel Architecture Software Developer's Manual: Basic Architecture, order number 243190, .COPYRGT.1996, 1997, hereby incorporated by reference in its entirety. Floating point optimization techniques for the Intel FPU are provided in Chapter 5 of Intel Architecture Optimization Manual, order number 242816-003, .COPYRGT.1996, 1997, hereby incorporated by reference in its entirety.
The mainstream development of compiler register allocation technology deals with registers with fixed names and not with stack registers. This existing technology does not deal with register stacks because as operations are performed on the register stack the values kept in the stack registers move around within the register stack.
It would be advantageous to provide a method, apparatus and program product that applies the prior art register allocation technology that deals with fixed-name registers to registers organized as a register stack.